Magnetic core matrix switch



Sep 1965 J. K. SHORTLE ETAL MAGNETIC CORE MATRIX SWITCH Filed April 13, 1961 FIG. 2

EE LL T mmm H M A V U E mw Mm Y B T IF E 0 b m W F F H E M F E H E V V AGENT United States Patent 3,208,043 MAGNETIC CORE MATRIX SWITCH Jack K. Shortle, Poughkeepsie, N.Y., and Russell A. 'Rowley, Saratoga, Califl, assignors to International Business Machines Corporation, New York, N.Y., a

corporation of New York Filed Apr. 13, 1961, Ser. No. 102,737 4 Claims. (Cl. 340166) This invention relates to coincident current matrix switches and, more particularly, to an output circuit for such a switch which is devised to eliminate half-select noise currents. I

Switching devices capable of applying power to any of a plurality of loads find many uses in the electrical arts. One example of such use is in the control of a magnetic core memory array of the type employed in modern data processing machines. Such arrays generally include at least one plane provided with separate row windings, each inductively coupling a row of cores; and separate column windings, each inductively coupling a column of cores. More than one plane may be employed to increase the storage capacity of the array. Excitation of both the selected row and the selected column winding of a plane causes the core at the intersection of these windings to have its magnetic condition changed.

Selection of a row winding or a column winding in such an array may be accomplished by a coincident current matrix switch, such as that shown in Patent 2,734,187, entitled Static Magnetic Matrix Memory, filed by J. A. Rajchman December 29, 1951, or by an anti-coincident current matrix switch such as that shown in FIG. 4 of Patent 2,947,977, entitled Switch Core Matrix, filed by E. Bloch June 11, 1956. Each of these switches bears a strong resemblance to the array plane it is driving. The switch for the row drive windings, for example, contains a number of magnetic cores equal to the number of rows in the driven array plane. The cores in each row and each columns of the switch are inductively coupled by separate row and column input windings, and a switch (drive) core has its magnetic condition changed in response to the joint excitation of the row and column input windings which link it. The output winding of each drive core is connected in series with a related memory array row or column winding.

While the bistable magnetic cores possessing low saturation inductance employed in the switch will be driven from a first state of remanent induction to a second state of remanent induction only in response to the combined action of exciting currents on the row and column windings coupling it, the appearance of a current on either of these input windings will cause a certain amount of flux change in the core. Thus, in addition to the large flux change in the selected core of the switch, there will be small flux changes in all of the other cores linked by the selected row and column input windings. These small flux changes will induce undesired noise current in the drive windings connected in series with the output windings of these cores which will in turn cause undesired flux changes in the memory cores they couple. These flux changes will induce noise currents in the memory sense winding and may, if large enough, cause stored in formation to be lost. This danger of information loss is particularly acute in memory cores at the intersection of such a noise containing drive windings and an energized drive winding.

It is therefore apparent that some method of cancelling these noise signals is desirable. One method presently used to solve this problem is to provide two common lines for each plane of the switch. The series combinations of switch-core output windings and memory plane drive 3,208,043 Patented Sept. 21, 1965 windings are connected in parallel between these two common lines. With this arrangement, the only return path for current flowing in the selected drive winding is through the other drive windings of the plane. If I is the drive current flowing through the selected drive winding and N is the number of drive windings connected in parallel, a current equal to I/N-1 will flow in each of the unselected drive windings tending to cancel the noise currents developed therein. But, with R equal to the total impedance of the memory cores being driven by a given drive winding, the load faced by the selected switch core is increased by R/N1 and, therefore, the current rise time is increased.

It is, therefore, an object of this invention to provide an improved circuit for eliminating half-select noise in the output windings of a coincident current matrix switch.

It is a further object of this invention to provide a circuit of the type described above which will result in a minimum increase in the load faced by the selected switch core.

In accordance with these objects, this invention employs a circuit which is similar to that mentioned above in that there are two common lines for each plane of the switch with the series combination of the drive core output windings and the memory array drive windings connected in parallel between these two common lines. The drive windings serve as loads for their series connected output Windings. To this combination is added an inductive element connected between the two common lines in parallel with the output winding drive winding combinations. For maximum noise cancellation, the inductance of this element is, for one embodiment of the invention, selected to be of a value such that the potential drop across it caused by the return of current from the selected drive winding through it will be substantially equal to the potential developed across the output windings of the halfselected cores. With this circuit configuration, the net potential about any closed loop, except one containing the selected drive windings, is effectively equal to zero. Therefore, no current will flow in these loops. Since the inductive element presents a high impedance only to AC. signals, it provides a short circuit path for drive current of the selected drive winding once steady state conditions have been attained and, therefore, does not greatly increase the load faced by the selected drive core.

In an alternative embodiment of the invention, the above result is achieved by placing an extra magnetic core in the switch plane, this core being driven only by the common drive winding of the plane, and placing the output winding of this core in parallel with the other output windings of the plane but inserting no load in series with this output winding.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

FIGURE 1 is a schematic diagram of an output circuit for a coincident current matrix switch employing the concepts of this invention. The diagram shows one plane of the output circuit in detail and a second plane of the output circuit in outline.

FIGURE 2 is a hysteresis curve of a drive core such as might be employed in the circuit of this invention.

FIGURES 3a and 3b are graphic representations of the output potential from a half-selected and a fully-selected drive core, respectively, drawn to a common time scale.

FIGURE 4 is a schematic diagram of a portion of an output circuit for alternative embodiment of this invena tion.

Referring to FIG. 1, it is seen that the coincident current matrix switch shown has a slightly different input winding pattern than that used in the beforementioned Rajchrnan patent; however, this dilierence results mainly from the fact that the switch of FIG. 1 is designed to drive a multi-plane memory array whereas the Rajchman switch is designed to drive only a single-plane memory. The following discussion will be with reference to one plane of a coincident current switch, but it should be kept in mind that this invention may also be applied to an anticoincident current switch and that, in a practical circuit, there will be as many planes in the switch as there are in the memory array. A second plane has been shown in outline in FIG. 1 to illustrate the limited interaction between planes.

The switch is made up of a plurality of bistable magnetic cores 10,40 each of these cores having a hysteresis curve of the type shown in FIG. 2. A bias winding (not shown) having a steady state current applied thereto passes through all the cores of the switch, causing the cores to normally operate at point S far in the negative saturation region of the hysteresis curve. Each drive core also has passing therethrough a row input winding 12, a column input' winding 14 (only one of which is shown in FIG. 1), and output winding 16,46 Each output winding has connected in series therewith the drive winding for a row or column of the matrix memory array; these drive windings form the load for the drive cores and are indicated in FIG. 1 as inductor-resistor combinations 18 -18 The output-winding-drive-winding combinations for each plane are connected in parallel between two common lines 20 and 22. A line 23 containing only an inductance element 24, the value of whichwill be determined later, is also connected between common lines 20 and 22. I

From FIG. 1, it is seen that input winding 12 links all the cores in one plane of the switch. A signal applied to this winding will drive each of these cores from point S (FIG. 2) to point H on its hysteresis curve. The resulting flux change B developed in these cores will induce a potential E (FIG. 3a) across the output winding 16 of each of these cores. The value of this output potential will be: 7

v c in EH dt where L zthe inductance of an individual drive core, and i zthe current flowing in input winding 12.

From FIG. 1, it can also be seen that each input winding 14 passes through one core from each plane of the switch. The signal applied to an input winding 14 also has sufficient energy to alone drive a core to point H on its hysteresis curve; but, when signals are applied simultaneously to the input windings 12 and 14, linking a single drive core, the core is driven to point P on its hysteresis curve. This causes an amount of flux B to be switched, inducing a potential E (FIG. 3b) across the cores output winding.

Assume now that the drive cores are all operating at point S on their hysteresis curve and that it is desired to obtain a positive output signal in output winding 16;, while obtaining no output signal in any other output winding of the switch plane. To accomplish this, input signals are simultaneously applied to input winding 12 and to the input winding 14 shown in FIG. 1. These input signals drive core 10 to point P (FIG. 2) on its hysteresis curve and drive cores 10 and 10,,10 to point H on their hysteresis curve. The resulting flux changes in these cores induce the desired output potential E across output winding 16 but also induce undesired half-select potentials E across the other output windings of the plane,

Where Lzthe inductance value of element 24, and i :the current flowing through selected drive line 18 By a proper selection of the inductance value L, the average value, E can be made equal to the average value of E or in other words:

Since the potentials of E, and E are in opposition, the sum of the potentials around any closed loop in the circuit not containing the selected drive line 18 will be equal to zero when the value of L is selected to make the magnitude of these potentials equal. the average value of the potentials around the closed loop which includes drive line 18,, and the inductance element 24 would be E -E :0. Likewise, the sum of the values of the potential around the closed loop in cluding drive line 18 and 18 would be equalto E E :0. Since the sum of the potentials around each of these loops is zero, no current can flow in these loops and current will therefore flow only in the loop which contains the selected drive line 18 (It should be noted that in a practical circuit the wave forms of E and E will not be the same and therefore, at some instants of time, some small current will flow in the loops containing element 24.)

. For the short time period until steady state conditions are reached, this current flow will cause a back current approximately equal to I /N to How in each of the unselected drive lines. These currents oppose and tend to cancel the half-select currents induced in these lines.

However, once steady state conditions have been reached, inductance element 24 will present substantially zero impedance to current I providing a nearly short circuit return path for this current. fore, serves to cancel the undesired half-select noise current with a minimum increase in the load presented to the fully-selected drive core.

A complete cycle of operation of the magnetic core matrix memory array generally demands of the driver, first, a read signal of one polarity and then a write signal of the opposite polarity. The circuit, as described so far, supplies only the read signal. A write signal of the opposite polarity is obtained when, at the termination of the input signals on input windings 12 and 14, the selected drive core is reset to point S on its hysteresis curve by the steady state bias current on the bias line (not shown). Accompanying this desired output signal E' (FIG. 3b) are half-select noise potentials E' (FIG. 3a) caused by the resetting of the half-selected cores. The inductor 24 serves to prevent these half-select potentials from causing undesired current flows in exactly the same manner as it operated to accomplish this purpose on the read half of the cycle; the only difference in the operation of the circuit on these two half cycles is that all the polarities are reversed.

Referring to FIG. 4, the same results woull be obtained, although in a slightly diiferent way,if the output winding 30 of a magnetic core 32 of the same type as drive cores 10,40, was used as the inductance element 24. This For example,

This circuit, thereextra core would have row input winding 12 passing through it but would have no column input winding 14. Since this core has a hysteresis curve such as that shown in FIG. 2, a potential E would be induced across its output winding by current applied to winding 12. This potential would operate to cancel noise in the same way as the E potential induced across inductor 24, and, since the line 23 still contains only an inductance element, this line would still present substantially zero impedance to current I once steady state conditions had been attained.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

We claim:

1. A low noise matrix switch of the type comprising:

a plane of magnetic cores each linked by an individual drive winding and all linked by a common drive winding, whereby when one of the cores is switched by the combined action of half-select input currents on both of its drive windings, all of the other cores of the plane respond in a small degree to the half-select current on the common drive winding;

a plurality of parallel connected output circuits, one for each of said magnetic cores, each of said ouput circuits including an output winding linking the related core, and an individual load, said output windings having a potential developed across them which is a function of the currents applied to the drive windings of their respective cores;

said switch being characterized by low resistance return circuit means connected in parallel with said output circuits and including means for developing a voltage wave substantially coincident with, opposed to, and substantially equal in amplitude to the average potential of the voltage waves developed in the output windings of the cores which respond only to the half-select current on said common drive winding.

2. A low noise matrix switch of the type comprising:

a plane of magnetic cores each linked by an individual drive winding and all linked by a common drive winding, whereby when one of the cores is switched by the combined action of half-select input currents on both of its drive windings, all of the other cores of the plane respond in a small degree to the halfselect current on the common drive winding;

a plurality of parallel connected output circuits, one for each of said magnetic cores, each 'of said output circuits including an output winding linking the related core, and an individual load, said output windings having a potential developed across them which is a function of the currents applied to the drive windings of their respective cores;

said switch being characterized by low resistance return circuit means connected in parallel with said output circuits and including an inductance element for developing a voltage wave substantially coincident with, opposed to, and substantially equal in amplitude to the average potential of the voltage waves developed in the output windings of the cores which respond only to the half-select current on said common drive winding.

3. A low noise matrix switch of the type comprising:

a plane of magnetic cores each linked by an individual drive winding and all linked by a common drive winding, whereby when one of the cores is switched by the combined action of half-select input currents on both of its drive windings, all of the other cores of the plane respond in a small degree to the halfselect current on the common drive winding;

a plurality of parallel connected output circuits, one for each of said magnetic cores, each of said output circuits including an output winding linking the related core, and an individual load, said output windings having a potential developed across them which is a function of the currents applied to the drive windings of their respective cores;

said switch being characterized by low resistance return circuit means connected in parallel with said output circuits and including means for developing in response to the switching of one of said cores, a voltage wave substantially coincident with, opposed to, and substantially equal in amplitude to the average potential of the voltage waves developed in the output windings of cores which respond only to the half-select current on said common drive winding.

4. A low noise matrix switch of the type comprising:

a plane of magnetic cores each linked by an individual drive winding and all linked by a common drive Winding, whereby when one of the cores is switched by the combined action of half-select input currents on both of its drive windings, all of the other cores of the plane respond in a small degree to the halfselect current on the common drive winding;

a plurality of parallel connected output circuits, one for each of said magnetic cores, each of said output circuits including an output winding linking the related core, and an individual load, said output windings having a potential developed across them which is a function of the currents applied to the drive 7 windings of their respective cores;

said switch being characterized by low resistance return circuit means connected in parallel with said output circuits and including a winding linking an additional magnetic core linked by said common drive winding, the winding of said additional core developing a voltage wave substantially coincident with, opposed to, and substantially equal in amplitude to the average potential of the voltage waves developed in the output windings of said other core when the half-select current is received on said common drive winding.

References Cited by the Examiner UNITED STATES PATENTS 9/59 Counihan 340174 IRVING L. SRAGOW, Primary Examiner.

JOHN F. BURNS, Examiner. 

1. A LOW NOISE MATRIX SWITCH OF THE TYPE COMPRISING: A PLANE OF MAGNETIC CORES EACH LINKED BY AN INDIVIDUAL DRIVE WINDING AND ALL LINKED BY A COMMON DRIVE WINDING, WHEREBY WHEN ONE OF THE CORES IS SWITCHED BY THE COMBINED ACTION OF HALF-SELECT INPUT CURRENTS ON BOTH OF ITS DRIVE WINDINGS, ALL OF THE OTHER CORES OF THE PLANE RESPOND IN A SMALL DEGREE TO THE HALF-SELECT CURRENT ON THE COMMON DRIVE WINDING; A PLURALITY OF PARALLEL CONNECTED OUTPUT CIRCUITS, ONE FOR EACH OF SAID MAGNETIC CORES, EACH OF SAID OUTPUT CIRCUITS INCLUDING AN OUTPUT WINDING LINKING THE RELATED CORE, AND AN INDIVIDUAL LOAD, SAID OUTPUT WINDINGS HAVING A POTENTIAL DEVELOPED ACROSS THEM WHICH IS A FUNCTION OF THE CURRENTS APPLIED TO THE DRIVE WINDINGS OF THEIR RESPECTIVE CORES; SAID SWITCH BEING CHARACTERIZED BY LOW RESISTANCE RETURN CIRCUIT MEANS CONNECTED IN PARALLEL WITH SAID OUTPUT CIRCUITS AND INCLUDING MEANS FOR DEVELOPING A VOLTAGE WAVE SUBSTANTIALLY COINCIDENT WITH, OPPOSED TO, AND SUBSTANTIALLY EQUAL IN AMPLITUDE TO THE AVERAGE POTENTIAL OF THE VOLTAGE WAVES DEVELOPED IN THE OUTPUT WINDINTS OF THE CORES WHICH RESPOND ONLY TO THE HALF-SELECT CURRENT ON SAID COMMON DRIVE WINDING. 